The 2019 Semicon brought in many interesting developments. Intel hosted an event on semiconductor packaging. The slowdown in scaling conventional semiconductor fuels the need for packaging and communication between chips. This is to meet meet the expectations of IoT, Big Data, and AI markets. On the other hand, these markets are on the verge of exploding.
Key features characterizing a number of high current package designs are a move towards better SoC disaggregation and package level integration. Intel discussed its goals in semiconductor packaging in this event. Primarily, it will focus on developing a technology which can connect chips and chiplets in packages. Further, this complements the performance of monolithic SoCs.
By integrating technologies into packaging, Intel is targeting:
- Powerful delivery architectures
- Management of heat produced with high speed signaling
- Designs with heterogenous equipment from multiple sources
- Scaling of pitch and density for chip interconnects and
- Small footprint client product packages, such as smartphones and wearable devices
Heterogenous packaging offers a small electronic footprint, better performance, and improved energy efficacy. Nowadays, the packaging of semiconductors have become compact; slender packaging with smaller area for integrated electronics. However, producers often use to stack die and create structures on the back of the die for compact packaging. On the other hand. the options for performance are also increasing.
Most semiconductor transistors made today support various types of memory technologies, specifically NAND and DRAM. Further, advanced packaging technologies, like the ones Intel displayed in Semicon 2019, support dense and high-performance connections between processing and memory. Ed Doller from Doller Consulting Group said that the memory technology utilizes a majority of modern transistors in specific NAND and DRAM flash.